Low power displays are essential system components of most mobile electronic devices. The display subsystem is often one of the largest consumers of battery power as well as one of the most expensive components in many of these devices. The display industry has made continuous progress improving the visual performance, power consumption and cost through device and system architecture innovations. However, there is a class of important applications that require additional significant improvements in power and cost to become technically and financially viable.
The dominant display technology for mobile devices, computer monitors and flat panel TVs is currently amorphous silicon hydrogenated thin film transistor (a-Si:H TFT) liquid crystal, also known generally as active matrix LCD technology. Advanced manufacturing technologies support a highly efficient worldwide production engine with capacity of over 100 million square meters of flat panel displays per year. The most common display architecture in this technology consists of a simple array of TFT pixels on a glass panel that are driven by one or more driver ICs.
One significant barrier to building displays in a-Si:H TFT processes is the poor performance and long term reliability of the a-Si:H TFT devices. Compared to single-grain silicon CMOS technology a-Si TFTs have very low electrical mobility which limits the speed and drive capability of the transistors on the glass. Additionally, the a-Si TFT transistors can accumulate large threshold voltage shifts and subthreshold slope degradations over time and can only meet product lifetime requirements by imposing strict constraints on the on-off duty cycle and bias voltages of the transistors. “Electrical Instability of Hydrogenated Amorphous Silicon Thin-Film Transistors for Active-Matrix Liquid-Crystal Displays” and “Effect of Temperature and Illumination on the Instability of a-Si:H Thin-Film Transistors under AC Gate Bias Stress” give a good overview of the gate bias stress induced threshold shifts and subthreshold slope degradations seen in a-Si:H TFTs.
The positive and negative stress accumulation processes have very different accumulation rates and sensitivities to gate drive waveforms. To first order within the range of driving waveforms used in typical flat panel refresh circuitry, the accumulation of positive stress is not strongly dependent on the frequency content of the gate waveform and accumulates relatively rapidly as a function of the integrated “on” time and voltage of a given gate. As positive stress is applied the voltage threshold of the TFT device is typically increased. TFT circuits typically have a maximum allowable positive threshold shift beyond which the desired device functionality ceases.
Negative stress accumulation, in contrast, depends strongly on frequency in the range of frequencies normally used in flat panel displays, accumulating more slowly at higher frequencies. Negative stress accumulation typically manifests as both negative threshold shift and subthreshold slope degradation. For negative stress to have a significant affect, the gate of a typical a-Si TFT needs an unbroken stretch of negative bias (e.g. 100 ms or more for typical a-Si:H TFT devices). In conventionally scanned TFT flat panel displays, the gate voltage is positive only for a very small time (e.g. one line time, about 15 us every 16.600 ms frame; about 0.1% duty cycle) and negative for the rest of the frame period (e.g. 16.585 ms or about 99.9% of the frame period). Were it not for the strong frequency dependence of the negative stress, conventional 60 Hz panel drive would have a very short operational lifetime as negative stress accumulation would quickly render the display non-functional.
One of the key techniques to minimize system power of electronic systems is to limit or reduce the operation frequency. Power dissipation is often nearly proportional to refresh frequency in typical TFT LCD displays. In some applications where the displayed content does not require a fast optical response (e.g. slowly updated or static information) the power dissipation of a TFT LCD can be reduced significantly by driving the frame refresh at e.g. 1 Hz vs. a conventionally scanned 60 Hz. Such a reduction, while favorable for power, is problematic for the device. First, the optical quality of the display is compromised; at low frame rates the display can flicker significantly. Second, at low frame rates the negative stress accumulation of the pixel TFTs occurs much more rapidly than at 60 Hz and will quickly degrade the functionality of the display. As a result, while frame rate reduction from 60 Hz to 30 Hz or even 20 Hz has been used as a power reduction technique, TFT device reliability limits prevent further frame rate reductions in conventional displays. The display described herein addresses these limitations.
There are display applications where battery life of months or years is desired if not required e.g. electronic books, signs and price labels. A large set of new display technologies has been developed to address such markets that require little or no power between displayed content changes. Such displays are often referred to as electronic paper or bi-stable displays. This class of displays is primarily used in a reflective mode to minimize power. For devices whose primary utility is based on the display of information (e.g. mobile email, e-books, marketing messages) such utility is enhanced by display technologies that allow longer active display times between battery recharges or changes. The display described herein is directed to such applications.